The tasks will deal, for example, with FPGA-based acquisition and processing of digital signals, analog clock synchronisation and implementation of feed-forward systems. The ideal candidate will work in close contact with scientists in the group, but also independently, therefore a high motivation for improvement and self-study is essential.
Requirements:
- hands-on experience with RTL design and self-checking testbenches
- knowledge of either VHDL or/and Verilog (systemVerilog) hardware description languages
- experience with analog and digital signal processing as well as with RF componets
- knowledge of an high-level programming language (preferably Python)
Desired qualifications:
- experience in C/C++
- impedance-matched PCB design, signal integrity
- experience with design involving multiple clock domains
- TCL scripting
- high-speed (beyond 125 Msps) data acquisition systems
Application process
Please submit your application via email to walther-office@univie.ac.at as one single PDF.
- CV
- letter of motivation (no more than 1 page)
- contact details of 2 referees
Contact details
For further information, please contact Dr. Juan Loredo (juan.loredo@univie.ac.at) or the Walther group office (walther-office@univie.ac.at)
